COM 353 Microprocessors COM 353 Microprocessors Introduction
COM 353 Microprocessors COM 353 Microprocessors Introduction
COM 353 Microprocessors Lecture 3 Prof. Dr. Halûk Gümüşkaya Introduction to 8-bit Microprocessor Architecture and Operation [email protected] [email protected] http://www.gumuskaya.com Computer Engineering Department Tuesday, October 23, 2012 1 A Microprocessor Based System 1. Basic Microprocessor System Concepts 2. Microprocessor Architecture and Operation I 3. Intel 8085 Microprocessor SİSTEM YOLU 4. 8085 Microprocessor Based System 5. Isolated I/O Using IN and OUT Instructions ROM 6. Memory Mapped I/O 7. Programmable I/O and 8255 RWM Giriş Çıkış (Temel) (Temel) 3-durumlu buffer Latch, FF Programlanabilir Giriş/Çıkış Birimleri 8255, 8256 8253 (8254) 8251 8257 8259 8279, ... A collection of addressable registers: • Those registers reside within the microprocessor are internal registers, • and those exist in the ROM, RWM, and I/O ports are external registers. Typical Partial Set of System Bus Signals Name Function Number Direction* A31–A0 Address bus 16, 20, 24, 32, 36 Output D63–D0 Data bus 8, 16, 32, 64 Bidirectional RD Generalized read strobe 1 Output WR Generalized write strobe 1 Output IO/M Status (I/O or memory reference) 1 Output MEMR Memory read strobe 1 Output MEMW Memory write strobe 1 Output IOR Input device read strobe 1 Output IOW Output device write strobe 1 Output RESET System reset out 1 Output 3 Buses of a P-Based System CPU Mikroişlemcili Sistem Çip-üzeri yollar Saklayıcılar Yerel Sistem Yolu Hafıza ALU I/O I/O * Direction is specified with respect to the microprocessor. Harici Sistem Yolu Simple Input Port for a P-Based System Giriş Port'u Giriş Cihazı Latch 3-Durumlu Buffer E Veri Tutturma Darbesi Cihaz Seçme Lojiği Simple Output Port for a P-Based System Çıkış Port'u Sistem Veri Yolu D0 D1 Çıkış Cihazı Latch D0 D1 Dm Dm Giriş Cihazı Seçme Darbesi Çıkış Cihazı Seçme Darbesi A0 A1 Cihaz Seçme Lojiği An IO / M RD Sistem Veri Yolu A0 A1 An IO / M WR Internal Architecture 1. Basic Microprocessor System Concepts 2. Microprocessor Architecture and Operation R0 R1 ALU R2 3. Intel 8085 Microprocessor Genel Amaçlı Saklayıcılar 4. 8085 Microprocessor Based System (Arithmetic Logic Unit) R3 1. Control Unit 2. General Purpose Registers 5. Isolated I/O Using IN and OUT Instructions 3. Special Purpose Registers R3 6. Memory Mapped I/O Kontrol Birimi SR (Status Register) IR (Instruction Register) 7. Programmable I/O and 8255 4. Arithmetic Logic Unit 5. Other Special Units IP (Instruction Pointer) SP (Stack Pointer) Özel Amaçlı Saklayıcılar MAR (Memory Address Register) Teknolojinin gelişmesiyle eklenen diğer donanım ve yazılım MBR (Memory Buffer Register) (FPU, hafıza yönetim birimi, cache, ...) 1. Control Unit Simplified States of Control Unit Harici Veri Yolu It controls and synchronizes all data transfers and transformations in the microprocessor system. MBR Komut Saklayıcısı Dahili Veri Yolu IR Komut Kod Çözücü Kontrol Birimi Saat Dahili Saklayıcılara Kontrol Sinyalleri Bayraklar The output of the IR is decoded and used by the control unit to develop a sequence of microoperations (microistructions) and register transfers that execute the instruction. Komut mikroişlemcide Komut Okuma (Fetch) Yürütme (Execute) Komut yürütmesi biter Durma (HALT) Komutu RESET Durma (Halt) Donanım sıfırlaması olmadığı sürece dur RESET Harici Kontrol Girişleri Harici Kontrol Çıkışları Fetch Decode Execute Cycles Instruction Read an instruction from memory 2. General Purpose Registers They are used for storage, arithmetic and logic operations (x86), and addressing purposes. A (ACC) Fetch Instruction Intel 8085 registers Determine required operations Decode Operand The registers are used and operated upon either singly or in pairs Locate and obtain operand data Fetch Execute Result Store Next Instruction Compute result value or status X86 registers Write results to memory for later use Determine next instruction 3. Special Purpose Registers 4. Arithmetic Logic Unit • F (Flags) (8-bit status register, modified after an ALU operation) • PC (Program Counter – points to the next instruction to be executed in memory) • MAR (Memory Address Register) 8085 registers • MBR (Memory Buffer Register) • SP (Stack Pointer) AX BX CX DX DI SI A Temp. Reg BP SP X86 registers Internal Bus ALU ALU Flags Flags 8-bit ALU (8085) 16-bit ALU (8086/8088) Arithmetic and logic operations on one or two 8-bit, 16-bit (x86), and 32-bit (x86) operands are performed in this unit. Halûk Gümüşkaya 5. Other Special Units External Architecture FPU (Floating Point Unit) Cache Memory Memory Management Unit …. Address Bus Data Bus Control Bus 1. Bus control 2. Bus status 3. Interrupts 4. Bus arbitration 5. Coprocessor signaling 6. Misc The pins on a CPU chip Address Bus: Common address bus widths are 16, 20, 32, and 64 Data Bus: Common widths are 8, 16, 32, and 64. Control Bus: The control pins regulate the flow and timing of data to and from the CPU and have other miscellaneous uses. Control pins can be roughly grouped into the following major categories: Bus Control Interrupts Bus Arbitration Coprocessor Signalling Status Miscellaneous Control Bus Bus Control: Mostly outputs from the CPU to the bus telling whether the CPU wants to read or write memory or do something else. The CPU uses these pins to control the rest of the system. Status: They show the status (i.e. bus operation, MEMR, IOW) of CPU. Interrupts: They are inputs from I/O devices to the CPU. Bus Arbitration: These pins regulate traffic on the bus, in order to prevent two devices from trying to use it at the same time. Coprocessor Signalling: Some CPU chips are designed to operate with coprocessors such as floating point chips, graphics or other chips. Miscellaneous: CLK, XTAL, reset, power, … Internal Architecture of 8085A 1. Basic Microprocessor System Concepts INTR RST5.5 RST6.5 RST7.5 TRAP 2. Microprocessor Architecture and Operation INTA SID Kesme Kontrol SOD Seri I/O Kontrol 3. Intel 8085 Microprocessor 4. 8085 Microprocessor Based System A Geçici Reg. IR 5. Isolated I/O Using IN and OUT Instructions 6. Memory Mapped I/O C E H Komut Kod Çözücü ALU B D L SP PC 7. Programmable I/O and 8255 Bayraklar (F) X1 X2 CLK Üretimi READY X1 X2 RESET OUT SOD SID TRAP RST 7.5 RST 6.5 RST 5.5 INTR INTA AD0 AD1 AD2 AD3 AD4 AD5 AD6 AD7 VSS 1 2 40 39 3 4 38 37 5 6 36 35 7 8 34 33 9 10 11 12 13 8085A 32 31 30 29 28 14 15 16 27 26 25 17 18 19 24 23 22 21 20 (a) Vcc HOLD HLDA CLK (OUT) RESET IN READY IO/M S1 RD WR ALE S0 A15 A14 A13 A12 A11 A10 A9 A8 Adres Yolu A15 - A0 RST 6.5 RST 5.5 8 S0 S1 IO/M HOLD HLDA RIN ROUT INTR A15 - A8 A15 - A8 74LS373 ALE RD 8085A INTA HOLD HLDA Yol Hakemliği C OE SOD RESET IN RESET OUT CLK IO/M S0 S1 X1 X2 (b) Çeşitli ALE Adres Yolu A15 - A0 A7 - A0 AD7 - AD0 SID Yol Durum A15- A8 Adres Yolu Kesmeler Yol Kontrol WR READY MAR RESET 8085A RST 7.5 Veri Yolu D 7 - D0 RD WR ALE DMA MAR / MBR AD7- AD0 Adres/Veri Yolu Multiplexing of Address/Data Pins of 8085A TRAP 16 Durum Kontrol CLK OUT External Architecture of 8085A Zamanlama ve Kontrol Adres Latch'ı D7 - D 0 Veri Yolu 8085A Based System Machine Cycles and Timing Machine cycle: The fetching and execution of a single instruction. It consists of one more read/write operations (references) to memory or an I/O device. There are 7 different types of machine cycles in the 8085: Opcode fetch Memory read – MEMR Memory write – MEMW I/O Read – IOR I/O Write – IOW Interrupt acknowledge Bus idle Machine Cycle and State Information for the 8085A 3 status signals generated at the beginning of each machine cycle identify each type and remain valid for the duration of the cycle. Bus Status Bus Control Machine Cycle IO/M S1 S0 RD WR INTA Opcode fetch 0 1 1 0 1 1 Memory read 0 1 0 0 1 1 Memory write 0 0 1 1 0 1 I/O read 1 1 0 0 1 1 I/O write 1 0 1 1 0 1 Interrupt Ack. 1 1 1 1 1 0 Bus idle 0 1 0 1 1 1 DAD Ack. of RST, TRAP HLT 1 1 1 1 1 1 3-state 0 0 3-state 3-state 1 The Format of 8085 Instructions and Instruction Fetch Cycle The instructions consist of 1 to 3 bytes. Therefore, instruction fetch is 1 to 3 machine cycles The first machine cycle in an instruction cycle is always an OPCODE FETCH, and the 8-bits obtained during an OPCODE FETCH are always interpreted as the OP code of an instruction. The total number of machine cycles required varies from 1 to 5, with no one instruction cycle containing more than 5 machine cycles. Opcode Opcode Opcode Operand Operand1 Operand2 (a) (b) (c) (a) 1-byte (b) 2-byte (c) 3-byte 8085A instructions. Execution of STA and LDA Instructions Timing Values of 8085AH Microprocessor STA (Store Accumulator Direct) transfers the contents of ACC to an external register (a memory register or a memory mapped output register) whose address is specified in the instruction. The opcode for STA is 32h. This register can be located anywhere in the 64 K memory space that the 8085 can directly address, 16-bits are required for the address. LDA (Load Accumulator Direct) does the reverse operation. It reads from an external register to the ACC. The opcode is 3Ah. ADDR İşlem Kodu byte 1 ADDR + 1 Düşük Adres byte 2 ADDR + 2 Yüksek Adres byte 3 Processor Crystal MHz (fc) State Time ns (T) ADD Instruction (s) 8085AH-1 11.976 167 0.6680 8085AH-2 10.000 200 0.8000 8085AH-1 6.250 320 1.2800 8085AH-1 6.144 325.5 1.3000 STA veya LDA komutu 3-byte STA and LDA instructions Execution of STA and LDA Instructions Activities Associated with the T-States of 8085A Each machine cycle is divided by system clock into a number of state transitions, or T states, which correspond to the period between two negative going transition of that clock. T1 A memory or I/O device address is placed on the address/data bus (AD7-AD0) and address bus (A15-A0). An address latch enable, ALE, pulse is generated to facilitate latching the low order address bits on AD7-AD0. Status information is placed on IO/M, S1, and S0 to define the type of machine cycle. The halt flag is check. T2 Ready and hold inputs are sampled. PC is incremented if machine cycle is part of an instruction fetch. In all machine cycles except BUS IDLE, one of the control strobes –RD, WR, or INTAmakes a 1 to 0 transition. Tw (optional) This state is entered if the ready line is low. The states of the address, data and control signals remain the same as at the end of T2. T3 An instruction byte or data byte is transfered to/from memory the microprocessor. The active control strobe makes a 0 to 1 transition. T4 The contents of instruction register (IR) are decoded. T5 - T6 These states are used to complete the execution of some instructions. T-States of LDA and STA Instructions Machine Cycles T-States 1. Opcode fetch 4 2. Memory read 3 3. Memory write 3 4. Memory write (STA) or read (LDA) 3 Total T-states for 4 machine cycles 13 For STA and LDA instructions, the number of T-states required for the execution is 13. If the 8085 is operating at a 325.5 nS state time, the STA/LDA instruction cycle is executed in 4.23 S. Execution of IN and OUT Instruction IN InputPort IN reads the contents of an input device located at InputPort to the accumulator (ACC). The opcode for IN is DBh. InputPort is an 8-bit port address which is an operand in this instruction. 256 input ports are possible with this 8-bit port address. OUT OutputPort OUT does the reverse operation. It writes the contents of the ACC to the output port located at OutputPort. OutputPort is also an 8-bit address. This means 256 possible output ports. The opcode for OUT is D3h. ADDR İşlem Kodu byte 1 ADDR + 1 Port Adresi byte 2 IN veya OUT komutu 2-byte IN and OUT instructions Execution of IN and OUT Instruction 1. Basic Microprocessor System Concepts 2. Microprocessor Architecture and Operation 3. Intel 8085A Microprocessor 4. 8085 Microprocessor Based System 5. Isolated I/O Using IN and OUT Instructions 6. Memory Mapped I/O 7. Programmable I/O and 8255 System Memory System Memory Using Full Decoding The 8085 system has ROM and RWM memory modules, one input port (a simple 8-bit three-state buffer 74LS244) for reading switches, and one output port (74LS374) for driving a LED display. D7 - D0 Veri Yolu A11 - A0 0FFFh 1000h 17FFh 1800h 4K A15 0000h 0FFFh RWM - A11 A 12 0 0 0 0 0 0 0 0 - A8 0 0 0 0 1 1 1 1 2K Boş 1000h 17FFh 0 0 0 1 0 0 0 1 - A4 0 0 0 0 1 1 1 1 A3 - A0 0 0 0 0 0 1 1 1 0 0 0 0 1 1 1 1 A13 C Y0 A12 A11 B A Y1 0 0 0 0 1 1 1 1 4K ROM içinde bir hafıza hücresini seçer İlk 4K'lık bloğu seçer A7 IO / M A15 A14 G2A G2B G1 FFFFh 07FFh-0000h 17FFh-1000h Y2 Y3 A10 - A0 Y4 Y5 A11 - A0 11 Y6 Y7 D7 - D0 6116 2K x 8 RWM CS 0 0 0 0 1 1 1 1 RD WR OE WE 2K RWM içinde bir hafıza hücresini seçer Address Bit Map Memory Map A Simple Input Port at F0h (partial decoding) A Simple Output Port at F1h (partial decoding) +5V D7 D0 74LS244 Octal Buffer OE IO / M A7 A6 A5 A4 Cihaz Seçme Darbesi F0h Adresindeki Giriş Port'u +5V D7 S7 1 1 1 1 1 0 0 0 +5V RD OE 0FFFh-0800h 58K Üçüncü 2K'lık bloğu seçer D7 - D0 2732 4K x 8 EPROM CE RD 74LS138 0000h ROM A11 - A0 12 Use the memory system example given in the first lecture. 4K8 EPROM ve 2K8 RWM EPROM starts from 0000h, after EPROM RWM starts. D0 +5V WR Anahtar bilgisi F8h S0 D7 74LS374 Octal FF D0 CLK OE IO / M A7 A6 A5 A4 A0 Cihaz Seçme Darbesi F1h Adresindeki Çıkış Port'u Simple System Test Program at ROM IN CMA STA LDA OUT HLT F0h 1000h 1000h F1h Execution of In F0h Instruction ; F0h adresli giriş port'undan oku ((ACC) <- (F0h)). ; Okunan verinin bit'lerini tersle ((ACC) = (ACC)'). ; ACC'yi RAM'ın 1000h nolu hücresine yaz. ; RAM'ın 1000h nolu hücresinden ACC'ye oku. ; F1h adresli çıkış port'una yaz ((ACC) -> (F1h)). ; Program yürütmesini durdur. ADRES VERİ Program Assembly and Machine Code 0000h DBh Address Machine Code Assembly Code 0001h F0h 0000 DB F0 IN 0002h 2Fh 0003h 32h 0004h 00h 0005h 10h F0h 0002 2F CMA 0003 32 00 10 STA 1000h 0006 3A 00 10 LDA 1000h 0006h 3Ah 0009 D3 F1 OUT F1h 0007h 00h 000B 76 HLT 0008h 10h 0009h D3h 000Ah F1h 000Bh 76h KOMUTLAR IN F0h CMA STA 1000h LDA 1000h OUT F1h HLT Execution of STA 1000h Instruction Execution of Program in the 8085 Simulator Assembly Program and its Machine Code Registers EPROM and RWM Input and Output Ports Input and Output Address Spaces 1. Basic Microprocessor System Concepts 2. Microprocessor Architecture and Operation 3. Intel 8085A Microprocessor 4. 8085 Microprocessor Based System 5. Isolated I/O Using IN and OUT Instructions 6. Memory Mapped I/O 7. Programmable I/O and 8255 IN PortNumber instruction Read from an input port located at PortNumber to the accumulator (ACC) [PortNumber]. PortNumber = 00h FFh: 256 input ports OUT PortNumber instruction Write the contents of ACC to an output port located at PortNumber. Again 256 output ports. I/O Decoding of Control Lines and Addresses The corresponding IO/M, RD, WR signals are generated when these instructions are executed by the CPU. These signals and some address lines are used by the decoding logic to access the I/O ports. I/O Address Spaces and Ports Since there are 2 different instructions for I/O access, two different address spaces exist for I/O operations. Totally 512 ports (8085) 1. Basic Microprocessor System Concepts 2. Microprocessor Architecture and Operation 3. Intel 8085A Microprocessor 4. 8085 Microprocessor Based System 5. Isolated I/O Using IN and OUT Instructions 6. Memory Mapped I/O 7. Programmable I/O and 8255 I/O Devices at Memory Address Space I/O devices are located at memory address space. Use memory related instructions (like LDA, STA) to access I/O devices. The I/O decoders monitor memory related control lines and addresses. An Input Device at a Memory Address To access an input port, use a memory access instruction, like LDA The input decoder monitors memory related control lines and addresses. An example: An input device is located at a memory address F000h. Use partial address decoding, use just 4 address lines from the address bus: A15, A14, A13, and A12. +5V MEMR IO / M RD A15 A14 A13 A12 F000h Adresindeki Giriş Port'unu Seçme Darbesi An 8-input NAND gate is used as an input decoder. The input device is located at F000h. When IN F000h is executed by CPU, at the last machine cycle, F000h is placed onto the address bus, IO/M becomes 0. Finally RD is activated low, and an active low signal is generated by the NAND gate. As a result of this pulse, the 3-state buffer of the input device is activated, and data at this device is read to ACC by CPU. An Output Device at a Memory Address To write to an output port, use a memory access instruction, like STA. The output decoder monitors memory related control lines and addresses. An example: An output device is located at a memory address F001h. Use partial address decoding, use just 5 address lines from the address bus: A15, A14, A13, A12, and A0. +5V MEMW IO / M WR A15 A14 A13 A12 A0 F001h Adresindeki Çıkış Port'unu Seçme Darbesi An 8-input NAND gate is used as an output decoder. The output device is located at F001h. When OUT F001h is executed by CPU, at the last machine cycle, F001h is placed onto the address bus, IO/M becomes 0. Finally WR is activated low, and an active low signal is generated by the NAND gate. As a result of this pulse, the input device is activated, and 8-bit data at ACC is written to the output device by CPU. Memory and I/O Address Spaces Why Memory Mapped I/O ? Some processors may not have such separate IN and OUT instructions for I/O in their instruction set. Using IN and OUT, you can only read from or write to an I/O device. If you want to do some other operations, like OR, AND, ADD, …) directly on I/O devices, the memory mapped I/O technique can be used. If the number of I/O devices is larger than 512 (for 8085) use the memory mapped I/O. 1. Basic Microprocessor System Concepts 2. Microprocessor Architecture and Operation 3. Intel 8085 Microprocessor 4. 8085 Microprocessor Based System 5. Isolated I/O Using IN and OUT Instructions 6. Memory Mapped I/O 7. Programmable I/O and 8255 Programmable I/O In our previous simple example, we had very simple I/O devices. In general microprocessor based systems, like PCs, have programmable I/O devices. These devices have programmable I/O ports. In addition to simple reading and writing data, they have also some build-in additional features, like timers/counters, interrupts, bit-addressable ports, … Some examples: Basic and handshake parallel I/O (8255, 8256) Timer/counter (8253/8254) Interrupt controller (8259) Serial/parallel data communication (8250, 8251, 8256) 1-bit data I/O (bit addressable) (8256) Keyboard/display interface (8279) Block data transfer between memory and external world (DMA) (8257) 8255 IC (a) and Logic Diagram (b) 1 2 40 39 PA4 PA2 PA1 PA0 3 4 38 37 PA6 PA7 RD CS 5 6 36 35 WR RESET GND 7 8 34 33 D0 9 10 32 31 PA3 A1 A0 PC7 PC6 PC5 PC4 PC0 PC1 PC2 PC3 PB0 PB1 PB2 11 12 13 8255A 30 29 28 14 15 16 27 26 25 17 18 19 20 24 23 22 21 PA5 Veri Yolu D0 - D7 D1 D2 D3 D4 D5 D6 D7 VCC PB7 PB6 8255A A1 A0 PB5 PB4 PB3 RESET Programmable pripheral device PC CS RD WR (a) PA PB (b) 4 addresses are occupied in I/O space D7-D0 Data Bus (bidirectional) PA7-PA0 Port A PB7-PB0 Port B PC7-PC0 Port C CS Chip Select A0, A1 Port Address RD Read Control WR Write Control RESET Reset Input VCC +5 Volt GND 0 Volt 8255A Chip and Port Select Signals CS A1 A1 Selected Port 0 0 0 Port A 0 0 1 Port B 0 1 0 Port C 0 1 1 Control Register 1 X X 8255A not selected 8255A at C0h and its Select Logic 8255 Control Word Kontrol Kelimesi D7 - D 0 D7 - D0 PA D7 0/1 PA = C0h D6 D5 D4 D3 D2 D2 D0 D7 D6 D5 D4 D3 D2 D1 D0 Grup B Kontrol Kelimesi Port C (Düşük PC 3 - PC0) 1 = Giriş 0 = Çıkış +5V BSR Modu (Bit Set/Reset) A7 PB A6 PB = C1h CS A5 A4 A3 A2 A1 A1 A0 A0 IOR RD IOW WR A ve B port'ları etkilenmez PC CS = 0 A7 A6 A5 A4 A3 A2 1 1 0 0 0 0 C Port'u üzerinde tek bit 0'lama ve 1'leme yapılır Mod 0 Mod 1 A, B ve C port'ları için basit giriş/çıkış PC = C2h Address A1 A0 0 0 0 1 1 0 1 1 = = = = C0h C1h C2h C3h Port B 1 = Giriş 0 = Çıkış I / O Modu Mod Seçimi 1 = Mod 0 0 = Mod 1 Mod 2 A ve (veya) B port'ları için el sıkışmalı (handshake) çalışma A port'u için iki yönlü veri yolu Grup A Port B: Mod 0 veya 1 de çalışır Port C (Yüksek PC 7 - PC4) 1 = Giriş 0 = Çıkış C port'u el sıkışma sinyalleri için kullanılır C port'unun bit'leri el sıkışma sinyalleri olarak kullanılır Port A 1 = Giriş 0 = Çıkış Mod Seçimi 00 = Mode 0 01 = Mod 1 1X = Mod 2 Selected Port 1 = I/O Modu 0 = BSR modu PA PB PC Control Register 8255 for the 8085 Based System of using a 3-state buffer and a latch for I/O devices, this time use an 8255 for the 8085 based system example. 8255 base address is F0h, that is the address of PA. PA will be used to read switches. PB (at F1h) will be used to drive the LED display. PC (at F2h) will not be used. Control register is at F3h. Control word = 1 0 0 1 0 0 0 0 = 90h. I/O Operations Using 8255 Instead +5V 8255A Veri Yolu D0 - D7 D0 - D7 PA +5V IO / M A7 A6 A5 A4 CS A1 A1 A0 A0 RD RD S7 1 1 1 1 1 0 0 0 D7 S0 +5V PB WR WR RESET D0 PC A simple I/O example using a 8255 located at F0h. MVI A, 90h OUT F3h ; (ACC) 90h, Load ACC with 90h (A: input, B: output) ; (F3) (ACC), write the contents of ACC (90h) to control register, 8255 is programmed. IN F0h; OUT F1h ; read switches (ACC) (F0h) ; drive LEDs (F1) (ACC) References Mikroişlemciler ve Bilgisayarlar, 3. Basım, H. Gümüşkaya, ALFA, 2002. (Chapter 3).