özgeçmiş ve eserler listesi özgeçmiş

ÖZGEÇMİŞ VE ESERLER LİSTESİ
ÖZGEÇMİŞ
Adı Soyadı: Sezer GÖREN UĞURDAĞ
Öğrenim Durumu:
Derece
Bölüm/Program
Üniversite
Yıl
Lisans
Elektrik Elektronik Müh.
Boğaziçi Üniversitesi
1993
Y. Lisans
Elektrik Elektronik Müh.
Boğaziçi Universitesi
1995
Doktora
Bilgisayar Müh.
University of California, Santa
Cruz, ABD
2003
Temel Alan: Mühendislik
Doçentlik
2011
Bilim Alanı: Bilgisayar-BiliĢim Bilimleri Mühendisliği
Yüksek Lisans Tez Başlığı (özeti ekte) ve Tez Danışmanları :
VLSI Design and Implementation of Morphological Filters.
Sina BALKIR ve Emin ANARIM.
Doktora Tezi Başlığı (özeti ekte) ve Danışmanı :
Finite State Machine Verification, Test, and Minimization.
Joel F. FERGUSON.
Görevler:
Görev
Unvanı
Ar.Gör.
Görev Yeri
Yıl
Müh. Fakültesi Elektrik Elektronik Müh. Boğaziçi Üniversitesi
1993-1996
AraĢtırmacı
Centre de Morphologie Math. Ecole des Mines Paris FRANSA
1996
Ar. Gör.
University of California, Santa Cruz, CA, ABD
1998-1999
Stajyer
Syntest, Sunnyvale, CA, ABD
1999
Uzman
Cadence, San Jose, CA, ABD
1999-2000
Uzman
Apple Computer, Cupertino, CA, ABD
2000
Uzman
PMC-Sierra, San Jose, CA, ABD
2001-2002
Uzman
Aarohi Communications (Emulex), San Jose, CA, ABD
2002-2004
Yar. Doç.
Müh. Fakültesi Bilgisayar Müh. BahçeĢehir Üniversitesi
2005-2010
AraĢtırmacı
University of California, Santa Cruz, CA, ABD
2006
Yar. Doç.
Müh. Fakültesi Bilgisayar Müh. Yeditepe Üniversitesi
2010-2011
Doç.
Müh. Fakültesi Bilgisayar Müh. Yeditepe Üniversitesi
2012-Halen
Yönetilen Yüksek Lisans Tezleri :
1.
2.
3.
4.
A. Çağatay CURA. Parking Spot Finder: An Automated Software Service with SMS
and Map Interface. 2009.
Ferhat CANBAY. Point Based Correspondenceless Pose Estimation. 2009.
Özgür Özkurt. FPGA Design Security with Time-Division Multiplexed PUFs (devam
etmekte)
Abdullah Yıldız. Secure, Remote, and Fast Multi-Boot of FPGAs (devam etmekte)
Projelerde Yaptığı Görevler :
1. AraĢtırmacı –Hdl Tool Kit. TÜBĠTAK Doktora sonrası AraĢtırma Bursu. University of
California, Santa Cruz, CA, ABD. 2006.
2. Lider (Tasarım Doğrulama) –Design Verification and FPGA prototyping of fabric based
storage application processing chip at wire speeds ranging from 1Gb to 10Gbps
across multi-protocol storage networks. Aarohi Communications (Emulex), San Jose,
CA, ABD. 2002-2004.
3. Lider (Tasarım Doğrulama) –System level design verification of network packet
processor chip. PMC-Sierra, San Jose, CA, ABD. 2001-2002.
4. Uzman (Yazılım Doğrulama) –Software Test of TestBuilder -High Level Design
Verification Tool. Cadence, San Jose, CA, ABD. 1999-2000.
5. Uzman (Yazılım Doğrulama) –Software Test of SignalScan -Waveform Viewer Tool
Software. Cadence, San Jose, CA, ABD, 1999.
6. AraĢtırmacı –Checking Sequence Generation for Flip-flops and Latches. MICRO
Projesi, University of California Santa Cruz, ABD, 1999.
7. AraĢtırmacı –Hardware Implementation of Advanced Morphological Filters. TÜBĠTAK
NATO-A2. Centre de Morphologie Mathematique, Ecole des Mines, Paris, Fransa,
1996.
Bilimsel Kuruluşlara Üyelikler :
ACM üyesi
IEEE üyesi
IEEE Test Technology Technical Council üyesi
Hakem, TÜBĠTAK TEYDEB hakemliği
TÜBĠTAK Elektrik Elektronik ve Enformatik AraĢtırma Grubu BiliĢim Paneli hakemliği
Program Komite Üyesi, IEEE NASA/ESA Conference on Adaptive Hardware and Systems
(AHS), 2012
Düzenleyici Komite Üyesi, 2011 International Conference on High Performance
Computing & Simulation (HPCS), 2011
Düzenleyici Komite Üyesi, International Wireless Communications and Mobile Computing
Conference (IWCMC), 2011
Program Komite Üyesi, Intl. Symposium on Computer and Information Sciences (ISCIS),
2011
Program Komite Üyesi, IEEE NASA/ESA Conference on Adaptive Hardware and Systems
(AHS), 2011
Program Komite Üyesi, IEEE Intl. Conference on Design and Technology (IDT), 2010
Bilim Kurulu Üyesi, Yıldız Teknik Üniversitesi Yıldızlı Projeler YarıĢması, 2010
Program Komite Üyesi, Intl. Symposium on Computer and Information Sciences (ISCIS),
2010
Program Komite Üyesi, IEEE Intl. Conference on Design and Technology (IDT), 2009
Program Komite Üyesi, IEEE Intl. Design and Test Workshop (IDT), 2007
Program Komite Üyesi, IEEE NASA/ESA Conference on Adaptive Hardware and Systems
(AHS), 2006
Hakem, TÜBĠTAK-TEYDEB
Panelist, TÜBĠTAK Elektrik Elektronik ve Enformatik AraĢtırma Grubu (EEEAG), 2009
Hakem, ICCAD
Hakem, European Test Symposium
Hakem, Elsevier Computers and Electrical Engineering
Hakem, Computer Journal
Hakem, MICRO program of California State, 2001-2003
Ödüller :
Milli Eğitim Bakanlığı YurtdıĢı Doktora Bursu.
NATO A2 AraĢtırma Bursu.
Üniversite GiriĢ Sınavı Türkiye kırkdördüncülüğü.
Fen Liseleri GiriĢ Sınavı Türkiye beĢinciliği.
Son iki yılda verdiği lisans ve lisansüstü düzeydeki dersler:
Akademik
Yıl
Dönem
Güz
2010-2011
Ġlkbahar
Güz
2011-2012
Ġlkbahar
Dersin Adı
Haftalık Saati
Teorik Uygulama
Öğrenci
Sayısı
Digital System Design
3
0
6
Real-Time Systems
3
0
9
Embedded Systems
Programming
Digital System Design
3
0
9
3
0
13
Principals of Logic Design
3
2
25
Digital Electronics
2
2
20
Real-Time Systems
3
0
8
Digital System Design
3
0
10
Digital Electronics
2
2
20
ESERLER
A. Uluslararası hakemli dergilerde yayımlanan makaleler :
A1. S. Gören, H. F. Ugurdag, O. Palaz. Defect-Aware Nanocrossbar Logic Mapping
through Matrix Canonization using Two-Dimensional Radix Sort. ACM Journal of Emerging
Technologies in Computing Systems, 7(3), article 12, 2011.
A2. H.F. Ugurdag, S. Gören, F. Canbay. Gravitational Pose Estimation. Computers and
Electrical Engineering, Elsevier. vol. 36(6), 1165-1180, 2010.
A3. S. Gören. Optimization of Embedded Controllers Based on Redundant Transition
Removal and Fault Simulation Using K-wise Tests. Journal of Circuits, Systems, and
Computers, 18(4), 647-663. 2009.
A4. S. Gören, A. Karahoca, F. Y. Onat, M.Z. Gören. Prediction of cyclosporine A blood
levels: an application of the adaptive-network-based fuzzy inference system (ANFIS) in
assisting drug therapy. European Journal of Clinical Pharmacology, 64(8), 807-814.
2008.
A5. S. Gören, F. J. Ferguson. On state reduction of incompletely specified finite state
machines. Computers and Electrical Engineering, 33(1), 58-69. 2007.
A6. S. Gören, F. J. Ferguson. Test sequence generation for controller verification and
test with high coverage. ACM Trans. Design Autom. Electr. Syst. 11(4), 916-938. 2006.
B. Uluslararası bilimsel toplantılarda sunulan ve bildiri kitabında (Proceedings)
basılan bildiriler :
B1. S. Gören, A. Yildiz, O. Ozkurt, H.F. Ugurdag. FPGA Bitstream Protection with PUFs,
Obfuscation and Multi-boot. International Workshop on Reconfigurable Communicationcentric Systems-on-Chip (ReCoSoC'2011). 2011.
B2. S. Gören, H.F. Ugurdag, and O. Palaz, Defect-Tolerant Logic Mapping for
Nanocrossbars Based on Two-Dimensional Sort, IEEE International Symposium on
Computer and Information Sciences. 2010.
B3. S. Gören, H.F. Ugurdag, A. Yildiz, O. Ozkurt. FPGA Design Security with Time
Division Multiplexed PUFs. IEEE International Conference on High Performance
Computing & Simulation (HPCS'2010). 2010.
B4. S. Gören, H.F. Ugurdag, O. Palaz. Defect-Aware Nanocrossbar Logic Mapping using
Bipartite Subgraph Isomorphism & Canonization. IEEE European Test Symposium
(ETS’10). 2010.
B5. H.F. Ugurdag, E. Argali, O.E. Eker, A. Basaran, S. Gören, H. Ozcan. Smart Question
(sQ): Tool for Generating Multiple-Choice Test Questions. WSEAS International
Conference on Education and Educational Technology (EDU'09). 2009.
B6. F. Ileri, S. Gören, H.F. Ugurdag, Virtual Smart Board. WSEAS International
Conference on Education and Educational Technology (EDU'09). 2009.
B7. H.F. Ugurdag, S. Gören, F. Canbay. Correspondenceless Pose Estimation from a
Single 2D Image using Classical Mechanics. IEEE International Symposium on Computer
and Information Sciences. 2008.
B8. S. Gören. A Meta-heuristic for Shared BDD Minimization. IFIP/IEEE International
Conference on Very Large Scale Integration (VLSI-SOC). 2008.
B9. S. Gören. Optimization of Interacting Controllers Using K-wise Tests, International
Design and Test Workshop (IDT), 169-174. 2007.
B10. H.F. Uğurdağ, Y. ġahin, O. BaĢkirt, S. Dedeoğlu, S. Gören, Y.S. Koçak. Populationbased FPGA Solution to Mastermind Game. NASA/ESA Conference on Adaptive Hardware
and Systems (AHS), 237-246. 2006.
B11. S. Gören, Using X-machines in Design Verification. International Research/Expert
Conference Trends in the Development of Machinery and Associated Technology (TMT).
2005.
B12. S. Gören, F.J. Ferguson. Testing Finite State Machines Based On a Structural
Coverage Metric. IEEE International Test Conference (ITC), 773-780. 2002.
B13. S. Gören, F.J. Ferguson. CHESMIN: A Heuristic for State Reduction of Incompletely
Specified Finite State Machines. IEEE/ACM Design Automation and Test in Europe
(DATE), 248-254. 2002.
B14. S. Gören, F.J. Ferguson. Checking Sequence Generation for Asynchronous
Sequential Elements. IEEE International Test Conference (ITC), 406-413. 1999.
B15. Pak K. Chan, M.J. Boyd, S. Gören, K. Klenk, V. Kodavati, R. Kundu, M. Margolese,
J. Sun, K. Suzuki, E. Thorne, X. Wang, J. Xu, M. Zhu. Reducing Compilation Time of
Zhong's FPGA-Based SAT Solver. IEEE Symposium on Field-Programmable Custom
Computing Machines (FCCM), 308-309. 1999.
B16. S. Gören, S. Balkir, G. Dündar, E. Anarim. Novel VLSI architectures for
morphological filtering. IEEE Workshop on Nonlinear Image and Signal Processing (NSIP),
875-878. 1995.
E. Ulusal bilimsel toplantılarda sunulan ve bildiri kitaplarında basılan bildiriler:
E1. S. Gören, H.F. Ugurdag, O. Ozkurt, A. Yildiz. PUF, DPSR ve Bulandırma Yoluyla
Sayısal Yongaların Güvenilir Yapılması. EMO 3. Ağ ve Bilgi
Güvenliği Ulusal
Sempozyumu. 2010.
E2. M. Z. Gören, S. Gören, A. Karahoca, F.Y. Onat. Terapötik Ġlaç Düzeyi Ġzlemi
Verilerine Veri Madenciliği Tekniklerinin Uygulanması Ġle Siklosporin A Kan Düzeylerinin
Önceden Tahmini. Türk Farmakoloji Derneği 19. Ulusal Farmakoloji Kongresi. 341-342.
2007.
E3. S. Gören, S. Balkır, G. Dündar, E. Anarım. Novel VLSI architectures for
morphological filtering (Türkçe). Sinyal ĠĢleme ve Uygulamaları Kurultayı (SIU), A:
Görüntü ĠĢleme. 187-192. 1995.
F. Diğer yayınlar :
F1. S. Gören. Hardware Implementation of Advanced Morphological Filters. Technical
Report. Centre de Morphologie Mathematique, Ecole des Mines, Paris, Fransa, 1996.
F2. S. Gören. HDL Tool Kit. Technical Report. SCTest, Baskin School of Engineering,
University of California, Santa Cruz. 2006.
F3. S. Gören, Abdullah Yıldız, Onur Demir. OMAPL138 Experimenter Kit Lab Manual.
2011.
ATIFLAR
A2. H.F. Ugurdag, S. Gören, F. Canbay. Gravitational Pose Estimation. Computers and
Electrical Engineering, Elsevier. vol. 36(6), 1165-1180, 2010. (Alıntılanma sayısı: 1)
1. M. Alarmel Mangai, N. Ammasai Gounden. Classification of 3-D objects and
faces employing view-based clusters. Computers and Electrical Engineering.
doi:10.1016/j.compeleceng.2011.08.007 (in press)
A4. S. Gören, A. Karahoca, F. Y. Onat, M.Z. Gören. Prediction of cyclosporine A blood
levels: an application of the adaptive-network-based fuzzy inference system (ANFIS) in
assisting drug therapy. European Journal of Clinical Pharmacology, 64(8), 807-814.
2008. (Alıntılanma sayısı: 2)
1. T. Uçar. Predicting existence of Mycobacterium tuberculosis on patients
using data mining approaches. Procedia. Elsevier. 2011.
2. E. G. Yıldırım. Dosage planning for diabetes patients using data mining
methods. Procedia. Elsevier. 2011.
A5. S. Gören, F. J. Ferguson. On state reduction of incompletely specified finite state
machines. Computers and Electrical Engineering, 33(1), 58-69. 2007. (Alıntılanma
sayısı: 10)
1. Hsu, Yating. Formal Analysis of Network Protocol Security. Doctor of
Philosophy, Ohio State University, Computer Science and Engineering, 2011.
2. Al Jassani, B.A.;
Urquhart, N.;
Almaini, A.E.A.; State assignment for
sequential circuits using multi-objective genetic algorithm. Computers &
Digital Techniques (IET). 2011.
3. A. Simao, A. Petrenko. Checking Completeness of Tests for Finite State
Machines. IEEE Trans. on Computers. 2010.
4. R.M. Hierons. Canonical finite state machines for distributed systems.
Theoretical Computer Science (Elsevier). 2010.
5. A. Alberto, A. Simao. Minimization of incompletely specified finite state
machines based on distinction graphs. Latin American Test Workshop. 2009.
6. G. Shu, Y. Hsu, D. Lee. Detecting Communication Protocol Security Flaws by
Formal Fuzz Testing and Machine Learning. Lecture Notes in Computer
Science. 2008.
7. Y. Hsu, G. Shu, D. Lee. A Model-based Approach to Security Flaw Detection of
Network Protocol Implementations. IEEE International Conference on Network
Protocols, 2008.
8. G. Shu. Formal methods and tools for testing communication protocol system
security. PhD dissertation, Ohio State University, 2008.
9. G. Shu. VCSTC: Virtual Cyber Security Testing Capability – An Application
Oriented Paradigm for Network Infrastructure Protection. Lecture Notes in
Computer Science. 2008.
10. A. Simao, A. Petrenko. Rapport technique Checking FSM Test Completeness
Based on Sufficient Conditions. CRIM-07/10-20 Collection scientifique et
technique. 2007.
B10. H.F. Uğurdağ, Y. ġahin, O. BaĢkirt, S. Dedeoğlu, S. Gören, Y.S. Koçak. Populationbased FPGA Solution to Mastermind Game. NASA/ESA Conference on Adaptive Hardware
and Systems (AHS), 237-246. 2006. (Alıntılanma sayısı: 1)
1. L Berghman, D Goossens, R Leus. Efficient solutions for Mastermind using
genetic algorithms. Computers and Operations Research (Elsevier). 2009.
B12. S. Gören, F.J. Ferguson. Testing Finite State Machines Based On a Structural
Coverage Metric. IEEE International Test Conference (ITC),
773-780. 2002.
(Alıntılanma sayısı: 2)
2. Q. Wu, M. S. Hsiao. Efficient Sequential ATPG Based on Partitioned Finite-State
Machine Traversal. International Test Conference. 2003.
3. C Hobeika, C Thibeault, JF Boland. Use of structural tests in RTL verification.
Microsystems and Nanoelectronics Research Conference. 2008.
B13. S. Gören, F.J. Ferguson. CHESMIN: A Heuristic for State Reduction of Incompletely
Specified Finite State Machines. IEEE/ACM Design Automation and Test in Europe
(DATE), 248-254. 2002. (Alıntılanma sayısı: 6)
1. A. Petrenko, N. Yevtushenko. Testing from Partial
Specifications. IEEE Trans. on Computers 54(9). 2005.
Deterministic
FSM
2. C.-H. Kim, S.-M. Jeong, G.-T. Hur, B.-G. Kim. Verification of FSM using
Attributes Definition of NPCs Models. International Journal of Computer
Science and Network Security 6(7A). 2006.
3. C.-H. Kim, S.-M. Jeong. Kinematic Access For Generation of Realistic Behavior
of Artificial Fish in Virtual Marine World. 2008.
4. Schmidt M. An Algorithm for Restriction of Finite Automata. Diploma Thesis,
Kaiserslautern Technical University. 2005.
5. A Barkalov, L Titarenko. Hardwired Interpretation of Control Algorithms.
Springer. Lecture Notes in Electrical Engineering: Logic Synthesis for FSMBased Control Units. 2009.
6. A Barkalov, L Titarenko. Synthesis of control units with field-programmable
logic devices. Springer. Lecture Notes in Electrical Engineering: Logic
Synthesis for Compositional Microprogram Control Units. 2008.
B15. Pak K. Chan, M.J. Boyd, S. Gören, K. Klenk, V. Kodavati, R. Kundu, M. Margolese,
J. Sun, K. Suzuki, E. Thorne, X. Wang, J. Xu, M. Zhu. Reducing Compilation Time of
Zhong's FPGA-Based SAT Solver. IEEE Symposium on Field-Programmable Custom
Computing Machines (FCCM), 308-309. 1999. (Alıntılanma sayısı: 7)
1. Pak K. Chan, MDF Schlag. New parallelization and convergence results for NC:
a negotiation-based FPGA router. ACM/SIGDA International Symposium on
Field Programmable Gate Arrays. 2000.
2. P Zhong, M Martonosi, P Ashar. FPGA-based SAT solver architecture with nearzero synthesis andlayout overhead. IEE Computers and Digital Techniques.
2000.
3. PK Chan, MDF Schlag, C Ebeling, L McMurchie. Distributed-memory parallel
routing for field-programmable gatearrays. IEEE Trans. on Computers. 2000.
4. I Skliarova, AB Ferrari. E&T, 2(6). 2002.
5. MJ Boyd, T Larrabee. ELVIS-Amortized Complexity Analysis of a Pipelined
Parallel Implication Circuit Using Single Cycle Paging. ACM/SIGDA
International Symposium on Field Programmable Gate Arrays. 2005.
6. S Ichikawa, L Udorn, K Konishi. An FPGA-based Implementation of Subgraph
Isomorphism Algorithm. meta.tutkie.tut.ac.jp
7. MJ Boyd. Complexity analysis of a massively parallel Boolean satisfiability
implication circuit. PhD Thesis. UCSC. 2005.
B16. S. Gören, S. Balkir, G. Dündar, E. Anarim. Novel VLSI architectures for
morphological filtering. IEEE Workshop on Nonlinear Image and Signal Processing (NSIP),
875-878. 1995. (Alıntılanma sayısı: 1)
1. J Kasperek. Real Time Morphological Image Contrast Enhancement in Virtex
FPGA. Lecture Notes in Computer Science. 2001.