INVESTIGATION IN GATE OXIDE INTEGRITY by ADAM JOHN

INVESTIGATION IN GATE OXIDE
INTEGRITY
by
ADAM JOHN WILLIAMSON, B.S.E.E.
A THESIS
IN
ELECTRICAL ENGINEERING
Submitted to the Graduate Faculty
of Texas Tech University in
Partial Fulfillment of
the Requirements for
the Degree of
MASTER OF SCIENCE
IN
ELECTRICAL ENGINEERING
Approved
Richard Gale
Chairperson of the Committee
Tanja Karp
Accepted
John Borrelli
Dean of the Graduate School
December, 2006
ACKNOWLEDGEMENTS
I would like to thank everyone who contributed to this project, professors,
committee members, and foundry engineers who offered their knowledge and
expertise, without your help I could not have completed this thesis.
Above all I would like to thank my beautiful wife Mary Donahue and our two
perfect children, Noah and Daphne. You three make every moment in life
wonderful…
ii
TABLE OF CONTENTS
ABSTRACT ........................................................................................................................ v
LIST OF TABLES .............................................................................................................. vi
LIST OF FIGURES ........................................................................................................... vii
CHAPTER
I
INTRODUCTION...................................................................................................... 1
1.1 Description and Operation of a MOSFET ........................................................... 1
1.2 Gate Oxide Integrity (GOI).................................................................................. 4
1.2.1 Dielectric Strength & Qbd ........................................................................ 6
1.3 Testing Procedures............................................................................................... 8
1.3.1 Time-Dependant-Dielectric-Breakdown (TDDB) ................................. 9
1.3.2 Capacitance-Voltage Measurements (CV)............................................ 10
1.3.3 Atomic Force Microscopy (AFM) ......................................................... 19
II
PRODUCTION OXIDE CHARACTERIZATION ................................................. 23
2.1 Production Device Characterization .................................................................. 23
2.1.1 Capacitance-Voltage Results (CV) ......................................................... 24
2.1.2 Time-Dependant Dielectric Breakdown (TDDB) ................................ 30
2.2 Poly-dot Test Structure Characterization ....................................................... 34
2.2.1 Capacitance-Voltage Results (CV) ........................................................ 35
2.2.2 Time-Dependant Dielectric Breakdown (TDDB)................................... 39
iii
III
EXPERIMENTAL PROCESS MODIFICATIONS ................................................. 42
3.1 GATE-OX Furnace............................................................................................ 42
3.2 PRE-GATE Clean.............................................................................................. 48
3.3 GATE/PRE-GATE Combined Split.................................................................. 58
IV
CONCLUSION........................................................................................................ 61
RESOURCES .................................................................................................................... 63
APPENDIX
A
THE FERMI LEVEL AND BAND DIAGRAMS .................................................. 64
B
DESCRIPTION OF WAFER SCRIBE LINES....................................................... 68
iv
ABSTRACT
Consistent and dependable transistors are necessary for all integrated circuit
applications. Of particular interest is the gate silicon oxide (SiO2) region of the
transistor. Ramped current stress breakdown, capacitance-voltage measurements
(CV), time-dependent dielectric breakdown (TDDB), and atomic force microscopy
(AFM) were used to evaluate the reliability of a 12.2 nm thick thermally grown
transistor gate oxide. The data revealed that both decreasing furnace temperature and
using a less aggressive pre-gate clean greatly increased the quality of the Si02 gate.
v
LIST OF TABLES
1: CV thickness results – production material ............................................................... 29
2: CV thickness results – test vehicle.............................................................................. 38
3: Gas/Temp Flows........................................................................................................... 44
4: Fab 2 vs. Fab 1, wet process differences [6] [9] .......................................................... 48
5: Experimental wet process changes ............................................................................. 51
6: Final Experimental process change results................................................................. 58
vi
LIST OF FIGURES
1: MOS transistor ............................................................................................................... 2
2: NMOS operation in saturation [19] .............................................................................. 3
3: Transistor gate region [23] ............................................................................................ 5
4: Oxide Breakdown histogram [2] ................................................................................... 6
5: TDDB testing.................................................................................................................. 9
6: MOS Capacitor [19] ..................................................................................................... 10
7: Fermi Level of NMOS device [16] .............................................................................. 11
8: Fermi Level of NMOS device [16] .............................................................................. 12
9: Changing capacitance value with bias conditions ..................................................... 14
10: Typical CV characteristics for low and high frequency [18] .................................. 15
11: Various charge densities in oxide [17]...................................................................... 16
12: Temperature stress CV plot showing ion impurities [16]........................................ 17
13: Cause of CV plot shifting [18] ................................................................................... 18
14: CV plot showing interface charge density [18]........................................................ 18
15: Interface Roughness................................................................................................... 20
16: AFM cantilever .......................................................................................................... 20
17: Topographic AFM image ........................................................................................... 21
18: (a) Design layout and (b) Cross sectional schematics .............................................. 23
vii
19: Experimental test set-up (a) probe station (b) under the microscope .................... 24
20: CV sweep for NMOS device...................................................................................... 25
21: Temperature Stress CV sweep for NMOS device..................................................... 26
22: CV sweep for PMOS device ...................................................................................... 27
23: Temperature Stress CV sweep for PMOS device ..................................................... 28
24: TDDB NMOS device - Fab1 (red) vs. Fab2 (blue).................................................... 31
25: TDDB PMOS device - Fab1 (red) vs. Fab2 (blue) .................................................... 32
26: Electron trapping in oxide (PMOS device) .............................................................. 33
27: (a) Design layout and (b) Cross sectional schematics .............................................. 34
28: CV sweep a) Poly-dot psub b) Poly-dot nsub .......................................................... 37
29: a) No booming b) Blooming c) Guard rings ............................................................. 38
30: TDDB of Poly-Dots a) NMOS b) PMOS ................................................................... 40
31: Oxide Growth ............................................................................................................ 42
32: Simplified representation of a GATE-OX Furnace .................................................. 43
33: Fab1 load and unload process (a) gas flow and (b) temperature ............................. 45
34: Experimental Furnace process results....................................................................... 46
35: Overflow vs. Quick-dump Rinse .............................................................................. 49
36: Hood vs. Mercury ...................................................................................................... 52
37: Wafer roughness pattern........................................................................................... 53
viii
38: Standard Hood Split showing top-center-flat variation .......................................... 54
39: Hood C/U split results................................................................................................ 55
40: Mercury Pre-Gate Clean (C/U) split results ............................................................. 56
41: Cool Start vs OverFlowRinse .................................................................................... 57
42: (a) Design layout and (b) Cross sectional schematics .............................................. 59
43: Fermi-Dirac distribution [16].................................................................................... 64
44: Band Diagrams [16].................................................................................................... 65
45: Metal Band Diagrams [16]......................................................................................... 66
46: Intrinsic and n-type Fermi Levels [16] ..................................................................... 67
47: Parametric vs. Functional Test.................................................................................. 68
48: Location of scribe between individual die ............................................................... 69
49: Packaging individual die for Functional test............................................................ 70
ix
CHAPTER I
INTRODUCTION
The overall quality of transistors is one of the leading issues in MOS (Metal
Oxide Semiconductor) integrated circuits. This paper focuses on the gate-oxide layer
of the MOS transistor and contains a comprehensive discussion of its quality using a
12.2 nm thick thermally grown gate-oxide. However to fully understand the impact
of the gate-oxide layer it is important to review the transistors structure and
operation to see just how much of its performance depends on the quality of its gateoxide.
1.1 Description and Operation of a MOSFET
The MOS transistor is a voltage controlled current source created through a
semiconductor layering process. A simplified version of both NMOS and PMOS
devices are shown in Figure 1 below along with a corresponding circuit
representation. Structurally the transistor is composed of a bulk silicon substrate of
type n or p (phosphorous or boron doped respectively) shown with connection B. An
insulating layer of gate oxide is grown to isolate the polysilicon gate, with connection
G, from the substrate material. Finally two implanted regions of n or p type silicon are
added to created a source and drain area, connection S and D, respectively.
1
NMOS
PMOS
D
S
B
G
B
G
S
B
D
G
S
B
D
S
G
D
gate-oxide
gate
n+
Width
gate
n+
p+
p+
psub
nsub
Length
Length
Figure 1: MOS transistor
The fundamental principal of transistor operation is quite simple. For NMOS a
positive voltage is applied to the gate, this begins to draw minority carriers, i.e.
electrons, to the gate substrate interface, creating a conduction path between source
2
and drain. A positive voltage applied to the drain (with source at ground) sweeps the
electrons form source to drain creating ID, the fundamental current of interest in MOS
operation. This is illustrated below in Figure 2.
Gate = 0
Source
Drain
exponential
log (ID)
no channel
square
saturation
region
Gate = (+)
S = GND
D>G
subthreshold
conduction
ID
V
channel
I
Gate = VT
S = GND
D>G
ID
V
channel complete
V
Figure 2: NMOS operation in saturation [19]
Figure 2 is a MOS in saturation (the typical region of use). The drain potential
is always higher or equal to the gate potential for this condition. From the graph we
see that the ID rises exponentially at first, then square. It is at this transition point that
the transistor is considered to be “on”. The gate voltage at this point is considered the
threshold voltage VT. [19]
3
At this point the importance of the gate-oxides insulating properties can be
seen clearly. In theory the potential across the oxide draws carriers from the substrate
to create a conduction path between source and drain with no current flowing into
the gate. In reality however, some small amount of current does flow through the
gate. If there are defects present in the oxide this current can begin to grow quickly as
gate-voltage is applied. A set of criteria needs to be in place to identify the quality of a
gate-oxide and its potential to be a perfect insulator.
1.2 Gate Oxide Integrity (GOI)
Figure 3(a) below shows a more detailed three dimensional image of a
transistor with a closer look at the gate region using an actual scanning electron
microscope, SEM (b).
4
(a)
(b)
600 nm
Figure 3: Transistor gate region [23]
The gate oxide is the very thin black line circled in purple, the gate poly
silicon is the lighter rectangle formed on top of this black line. The reader can see the
massive scale difference between the effective channel length 600 nm and the
thickness of the gate, 12.2 nm.
From above it can seen the great physical length current must flow in a
transistor, in contrast to the extremely thin layer of oxide attempting to contain the
current flow to the substrate alone, and not into the gate. Any small defect in such a
thin layer of material could be catastrophic to the quality of the transistor. In order to
project the quality of an oxide under normal operating conditions, full time-
5
dependent reliability of the SiO2 (gate-oxide) layer should be analyzed. This should
include a complete charge-to-breakdown characterization of the oxide.
1.2.1 Dielectric Strength & Qbd
The dielectric strength of an oxide is the maximum electric-field strength that
can be applied before breakdown occurs. It is typically measured with a current
density ramp and expressed in units of V/m. The dielectric field strength of oxide is
10-12 MV/cm [2].
100
Breakdown
Frequency (%)
Mode C
60
Mode B
Mode A
20
0
6
Breakdown Field Strength (MV/cm)
Figure 4: Oxide Breakdown histogram [2]
6
12
Oxide field strength as related to reliability is commonly plotted in a
histogram, an example of which is shown Figure 4. With the independent variable
the breakdown field strength, and the dependant variable breakdown frequency.
Mode A failures are usually the result of gross processing mistakes (pin holes in the
oxide, direct shorts, tester error) and are not solely considered a result of poor oxide;
as such they will not be dealt with in this thesis. Mode C failures are called intrinsic
failures and are inherent to every device. They are related to natural oxide
deterioration. Oxide is gradually weakened by the passage of gate current. This
weakening over time permits a continuous conductive path. At some point current
will abruptly discharged through this path irreversibly breaking down the oxide.
Mode B failures are considered defect driven, commonly referred to as extrinsic
failure. Possible issues may be: contamination in the oxide film or substrate, surface
roughness, thickness uniformity (localized thin oxide regions), crystalline defects in
the substrate, or plasma-induced degradation.
Another excellent indication of oxide quality is Qbd, charge-to-breakdown. It
is typically measured with time-dependant-dielectric-breakdown (see section 1.3.1)
in units of C/cm2 (per area as opposed to dielectric strength given in thickness). Qbd is
the integral of injected current density from zero to the time-to-dielectric
breakdown:
7
Q BD = ∫
t BD
0
J
dt
(1)
Taking a constant applied current, Qbd is simply the product of the current
density and the time-to-dielectric breakdown:
Q BD = (t DB )( J const )
(2)
1.3 Testing Procedures
The Joint Electron Device Engineering Council (JEDEC) [16], provides three
standard tests for wafer level thin dielectric testing. The voltage ramp test (V-Ramp)
starts at the use condition voltage or lower and ramps linearly from this value until
oxide breakdown. The current density ramp test (J-Ramp) begins at a low value of
current and ramps linearly/exponentially until oxide breakdown. The constant
current test (Bounded J-Ramp), most commonly referred to as Time-DependantDielectric-Breakdown (TDDB) uses a single specified current density level and is
maintained there until oxide breakdown. TDDB along with Capacitance Voltage
measurements, provide the fundamental measurements used for testing in this thesis.
8
1.3.1 Time-Dependant-Dielectric-Breakdown (TDDB)
TDDB testing is a simple way to evaluate the quality of oxides of varying areas,
the output of which results in a numeric value for Qbd.
+
Jconst
forced
measured
poly
I
V
oxide
e- e- e- e- e- e- e- e- e- e- e- e- e- e- e- etDB
nsub
t
tDB
t
_
Figure 5: TDDB testing
As shown in Figure 5, a constant current density Jconst is applied at the gate of A
PMOS device (nsub) and the voltage across the oxide is measured. Majority carriers,
electrons in the case, are drawn to the oxide substrate interface. The current density
should be large enough to stress the oxide to breakdown, JEDEC recommends values
between 0.1 - 0.5 A/cm2 [3]. The time of breakdown is noted and Qbd is calculated
from equation 1. It is important that the stress polarity biases the device into the
accumulation region (discussed in section 1.3.2), this guarantees that the field is across
the oxide only and not the oxide and depletion region (also discussed in section 1.3.2).
The correct polarity is shown in Figure 5 for PMOS.
9
1.3.2 Capacitance-Voltage Measurements (CV)
The MOSFET can be considered a parallel plate capacitor separated by a
dielectric with єr, oxide in this case, with thickness t.
C=
εOA
d
A
d
C=
V
εoεr A
t
contact e- e- e- e- eoxide
+ + + + + + +
source
t
drain
p-sub wafer
Figure 6: MOS Capacitor [19]
This is illustrated in Figure 6. It is important to note that the source and drain
of the device be connected to ground to ensure a single potential across the substrate
side of the capacitor.
During a CV measurement the device under test (DUT), is connected as in
Figure 6 and a voltage is swept at the gate, from positive to negative in this case as the
p-sub (NMOS) is shown.
10
b) accumulation
a) equilibrium
p-type
Vr
M
O
S
M
+
O
+
+
+
+
S
x
EC-SiO2
qФS
qФM
EC
qVr
EC
EFM
qVr
Ei
EFM
EFS
Ei
EFS
EV
EV
Figure 7: Fermi Level of NMOS device [16]
Fermi diagrams (see Appendix A for more Fermi information) will give better
insight into the nature of what occurs during this applied sweep. For simplicity we
will examine a MOSFET with metal and p-type semiconductors in an ideal case work
functions ФM = ФS (this eliminates any band bending at equilibrium).ФM and ФN do not
change with applied voltage. With a reverse bias to the NMOS device, a negative
voltage applied at the gate shown in Figure 7, it can be seen that the substrate
majority carriers (holes) are drawn up to the oxide/substrate interface.
11
b) depletion
a) equilibrium
c) inversion
p-type
Vf
M
O
Vf
M
S
O
S
M
+
+
O e
ee-
+ S
+
+
x
EC-SiO2
qФS
qФM
EC
EC
EC
qVf
qVf
EFM
E
Ei
E
EFS
EFN
EFN
EFM
qVf
EV
EV
qVf
EFM
EV
Figure 8: Fermi Level of NMOS device [16]
The Fermi energy level of the metal is raised with respect to the
semiconductor that is e- energy is increased on the metal side (e- deposited on the
metal with and a corresponding positive charge on the semiconductor side). The
device is said to be operating in accumulation. With a forward bias, a positive voltage
at the gate of the NMOS shown in Figure 8, minority carriers (electrons) are drawn
up to the oxide/substrate interface. The Fermi level of the metal is depressed with
respect to the semiconductor, positive charge deposited on the metal with a
12
corresponding negative charge in the semiconductor. With an initial increase in
forward bias the device is in depletion operation with EFN (the effective Fermi energy
level of the n doped silicon) above EFM (the Fermi energy level of metal) but still less
than Ei (the intrinsic Fermi energy level of the undoped silicon). With a further
increase in forward bias the device enters inversion, EFN > Ei. The charge carrier
profile of the silicon near the oxide now appears N-type, seen in the inversion figure
above and circled in green. The best criterion for strong inversion is that the surface
should be as strongly n-type as the substrate is p-type.
With no current passing through the oxide, EF of the semiconductor can not
change.
n o = (n i )e (E F − E i )/kT
p o = (p i )e (Ei − E F )/kT
(3)
Therefore from equation (3) Ei must bend near the interface to accommodate the
change carrier profile near the interface [16]. Where no is the concentration of
electrons and po is the concentration of holes.
A typical graph of a CV plot is shown in Figure 10 with a visual representation of the
voltage sweeps positive and negative limits shown in Figure 9. Both are again
representative of a p substrate device.
13
inversion
accumulation
V+
V-
Poly
Coxide
Oxide
e- e- e- e- e- e- e- e-
psub
Cdepletion
++++
Poly
Oxide
Coxide
+++++++++
psub
Cmax =
ε oε r A
, in accumulation
thickness
Figure 9: Changing capacitance value with bias conditions
The maximum capacitance Cmax is measured in accumulation when the only
capacitance value present is across the oxide, the voltage is negative enough that the
capacitance is essentially constant and the CV curve slope is close to flat. There, the
oxide thickness can be extracted from the oxide capacitance. “High” and “Low”
frequency are with respect to the generation-recombination rate of the minority
carriers in the inversion layer. If the gate voltage is varied rapidly, the charge in the
inversion layer cannot change in response, and thus does not contribute to the
capacitance. Hence, the semiconductor capacitance is at a minimum corresponding to
a maximum depletion width [16].
14
Strong
accumulation
Depletion
Strong inversion
C
Low frequency
Cmax
Weak
inversion
Weak
accumulation
High frequency
Cmin
VTH
VG
Figure 10: Typical CV characteristics for low and high frequency [18]
If the capacitance value is measured using too low a frequency the
recombination-generation kinetics of the electrons in the inversion region can vary in
response to the voltage variations. The values collected will be a measurement of
variations in the inversion region rather than the depletion region, again displaying a
capacitance value of Cmax (dashed line) [16].
Abnormalities in the CV plot can be due to mobile ionic charge, trapped
charge in the oxide, fixed charge, or charge trapped at the oxide/substrate interface.
Each of these is show below in Figure 11 [18].
15
K+
Na+
(Q m)
Na+
+
x
+
x
++
- - (Q ot)
K+
+
x
+
x
+
x
+
x
+
x
(Q it)
+ (Q f)
x
Si02 - Oxide
Si0x - ?
Si - substrate
Figure 11: Various charge densities in oxide [17]
Mobile ionic charge (Q m) is due to ion contamination, commonly alkali
metals, incorporated into the oxide during growth or subsequent processing. Oxide
fixed charge (Q f) is believed to be a thin (<3nm) transition region between substrate
and oxide with excess silicon ions, silicon broken away from the lattice during
oxidation but not fully reacted with oxygen. Interface trapped charge (Q it) is a result
of unsatisfied bonds at the interface between amorphous silicon and ordered crystal
substrate, readily trapping electrons or holes. Imperfections in the Si02 layer can also
lead to Oxide trapped charge (Q ot) [18].
Calculating Qm is done from the CV plot in Figure 12. First a CV plot is
generated of the oxide at a fixed room temperature of 25OC. The temperature is raised
16
to 200OC, ion impurities are more mobile at a raised temperature, and a positive bias is
applied to the oxide gate while the substrate is held [16].
C
Cmax
Before Stress
After Negative Stress
V
+
V
-
After Positive Stress
Vgate
Figure 12: Temperature stress CV plot showing ion impurities [16]
The temperature is lowered to 25OC and the “positive stress” CV plot is
generated. The temperature is again ramped to 200OC, this time a negative bias is
applied. The mobile ion charge Qm is calculated by [16]:
Qm = Cmax * |(V+ - V-)|
(4)
The purpose of the high temperature positive and negative stress is to mobilize the
impurity ions and drive them toward the oxide-silicon interface, for positive bias, and
the oxide-gate interface, for negative bias as pictured in Figure 13.
17
Gate
Sub
Oxide
200OC
V+
Gate
200OC
V-
Na+
Sub
Oxide
Na+
K+
K+
Figure 13: Cause of CV plot shifting [18]
Accumulation
Depletion
Inversion
C
Low frequency
Cmax
Difference is attributed to fast
interface state density Dit
CLF
CHF
High frequency
VG
D it =
⎞
C C
1 ⎛ C max C LF
⎜⎜
− max HF ⎟⎟
q ⎝ C max − C LF C max − C HF ⎠
Figure 14: CV plot showing interface charge density [18]
18
Following negative bias, with all impurity ions drawn to the oxide-gate
interface, there are no longer additive influences on inversion, and the layer should
form with a slightly greater voltage, shifting the CV plot to the right. With the ions in
place at the oxide-silicon interface after positive bias, the resulting 25OC CV sweep
should shift to the left as it requires less positive voltage to create an inversion layer
[18].
Qit can be determined from the Figure 14, when a difference between the
lowest point in the low frequency plot and the high frequency plot is noticed. Dit is
the fast interface state density in cm-2eV-1 [18].
1.3.3 Atomic Force Microscopy (AFM)
Surface roughness can be a major cause of gate oxide failure. We have assumed
in the above diagrams an element of uniformity at the material interfaces. Figure 15
gives a better indication of the non-uniformity possible between materials. Sharp
transitions in surface uniformity, circled in red, can have significant charge densities
at their points and create localized areas of thin oxide. These areas can become hot
spots for current flow and thinner areas of oxide will likely create early breakdown.
One excellent method for roughness measurement is an Atomic Force Microscope
(AFM).
19
poly
oxide
p-sub
Figure 15: Interface Roughness
The AFM was invented by Binnig, Quate and Gerber in 1986, and is one of the
foremost tools for imaging, measuring and manipulating matter at the nanoscale [20].
The AFM has two distinct modes of operation. The first mode, which is the mode
used in this project, lightly touches a tip at the end of cantilever to a sample.
Figure 16: AFM cantilever
20
The instrument performs a scan dragging the tip over the sample, while the
apparatus measures the vertical deflection of the cantilever, Figure 16 , which
indicates the local sample height. The second mode operates by measuring attractive
or repulsive forces between the tip and the sample, the AFM derives topographic
images from measurements without the tip physically touching the sample [21].
When calibrated correctly the device can be accurate within pico-meters. Figure 17 is
one of many images taken post clean up (discussed in section 3.2). The process has left
the wafer with <1 nm of surface roughness and a visible rinse pattern.
Figure 17: Topographic AFM image
21
All “average roughness” measurements in this thesis come from the overall
average of a 5μm by 5μm square area (Figure 17), with measurement time typically
taking an hour per sample.
22
CHAPTER II
PRODUCTION OXIDE CHARACTERIZATION
2.1 Production Device Characterization
Initial measurements began with breakdown and CV data for scribe line (see
Appendix B for more about scribe lines) capacitors already in place on production
wafers for oxide quality measurements. Scribe test structures are shown in Figure 18.
contact - gate
contact - substrate
oxide
p-sub wafer
220 um
chuck
80 um
NMOS
contact - gate
contact - substrate
oxide
n-well
contact
chuck
PMOS
(a)
(b)
Figure 18: (a) Design layout and (b) Cross sectional schematics
23
2.1.1 Capacitance-Voltage Results (CV)
CV measurements were conducted on the Agilent hp4284A LCR meter (with ±
0.02 pF accuracy) to reveal oxide thickness and defects present, the test set up is
shown in Figure 19. A -5 to +5 DC ramped voltage was applied to both NMOS and
PMOS devices with a superimposed 100 mV p-to-p 10 kHz and 100 kHz signal. 4
wafers, 3 sites each: top-center-flat (12 sites total), of both NMOS and PMOS were
tested, the results of which are shown in Figures 20-23.
(a)
(b)
Figure 19: Experimental test set-up (a) probe station (b) under the microscope
24
60.E-12
50.E-12
Capacitance (F)
40.E-12
10kHz
100kHz
30.E-12
20.E-12
10.E-12
000.E+0
-6
-5
-4
-3
-2
-1
0
1
2
3
4
5
6
Voltage (V)
Volatge
Figure 20: CV sweep for NMOS device
Figure 20 shows high and low frequency plots for NMOS devices. The curves
shown are the average of the above mentioned 12 sites with a standard deviation of
less than 0.01pF – less than the expressed accuracy of the instrument. The curves
appear to match the theoretical prediction of standard high and low MOS CV plots.
25
60.E-12
50.E-12
25C
25C w/ 200C_pos_bias
25C w/200C_neg_bias
Capacitance (F)
40.E-12
30.E-12
20.E-12
10.E-12
000.E+0
-6
-5
-4
-3
-2
-1
0
1
2
3
4
5
6
Volatge (V)
Figure 21: Temperature Stress CV sweep for NMOS device
Figure 21 shows temperature stress plots for NMOS devices. The curves shown
are the average of the above mentioned 12 sites with a standard deviation of less than
0.01pF. The curves show no discernable ionic contamination matching the theoretical
prediction of shifting MOS CV plots due to impurities present.
26
60.E-12
50.E-12
Capacitance (F)
40.E-12
100kHz
30.E-12
10kHz
20.E-12
10.E-12
000.E+0
-6
-5
-4
-3
-2
-1
0
1
2
3
4
5
Volatge (V)
Figure 22: CV sweep for PMOS device
Figure 22 shows high and low frequency plots for PMOS devices. The curves
shown are the average of the above mentioned 12 sites with a standard deviation of
less than 0.01pF. The curves appear to match the theoretical prediction of standard
high and low MOS CV plots.
27
60.E-12
50.E-12
Capacitance (F)
40.E-12
25C
25C w/ 200C_pos_bias
25C w/200C_neg_bias
30.E-12
20.E-12
10.E-12
000.E+0
-6
-5
-4
-3
-2
-1
0
1
2
3
4
5
Volatge (V)
Figure 23: Temperature Stress CV sweep for PMOS device
Figure 23 shows temperature stress plots for PMOS devices. The curves shown
are the average of the above mentioned 12 sites with a standard deviation of less than
0.01pF. The curves show no discernable ionic contamination matching the theoretical
prediction of shifting MOS CV plots due to impurities present.
28
Table 1: CV thickness results – production material
psub
nsub
C ox = 51.03pF
C ox = 52.20pF
ε o = 8.854x10 −12
ε o = 8.854x10 −12
ε r = 3.82
ε r = 3.82
A = 17600 um
A = 17600 um 2
2
t ox = 11.44 nm
t ox = 11.67 nm
The CV plots reveal no defects and calculations of thickness using equation are less
than 10% deviant from the target 12.2 nm. Numeric results are shown in Table 1.
C ox =
εoεr A
t ox
(5)
As noted the accuracy of the tester is ± 0.02 pF, additionally the area of the capacitor
can vary slightly given with exposure time (although this is very strictly controlled).
It is estimated that the area is accurate to ± 40nm. Both worst case scenarios are still
within 10% of desired thickness and do not affect the calculated Dit values
significantly.
29
2.1.2 Time-Dependant Dielectric Breakdown (TDDB)
In establishing processes to evaluate and their effect on Qbd it was important
to establish a comparison between production oxide qualities from the Fab 2 foundry
against Fab 1. Wafer scribe structures from identical devices processed at the separate
locations were tested. A constant current of 70μA, corresponding to a density of
0.4A/cm2, is forced at the gate of the device while the well is held at ground. The
voltage across the resulting capacitor is measured as time progresses.
The curves in Figure 24 and 25 represent wafers processed in Fab 1 and Fab 2.
It can be seen easily that the average breakdown of the Fab 1 sites occurs sooner than
Fab 2 processed sites with higher average Qbd values. It is also important to note the
dashed box area of the Figures. If we inspect this area more closely, it can be seen
plainly that the voltage at a given time is on average greater for Fab 1 sites than that
for Fab 2 sites, giving rise to a steeper slope with regards to voltage increase. The
cause of which is discussed below.
30
20
18
16
Voltage (V)
14
12
Fab1-Series1
Fab1-Series2
10
Fab1-Series3
(a)
Fab1-Series4
Fab1-Series5
8
Fab2-Series1
Fab2-Series2
6
Fab2-Series3
Fab2-Series4
4
Fab2-Series5
2
0
0
10
20
30
40
50
60
70
time (s)
18
18
17
Voltage (V)
17
16
(b)
16
15
Q bd avg: 20.87 C/cm2
Std: 0.943
15
Q bd avg: 23.20 C/cm2
Std: 0.423
14
0
10
20
30
40
50
60
70
time (s)
Figure 24: TDDB NMOS device - Fab1 (red) vs. Fab2 (blue)
31
20
18
16
Voltage (V)
14
12
Fab1-Series1
Fab1-Series2
10
Fab1-Series3
(a)
Fab1-Series4
Fab1-Series5
8
Fab2-Series1
Fab2-Series2
6
Fab2-Series3
Fab2-Series4
4
Fab2-Series5
2
0
0
10
20
30
40
50
60
70
time (s)
18
18
17
Voltage (V)
17
16
(b)
16
15
Q bd avg: 21.23
C/cm2
15
Q bd avg: 23.91
C/cm2
14
0
10
20
30
40
50
60
70
time (s)
Figure 25: TDDB PMOS device - Fab1 (red) vs. Fab2 (blue)
32
A closer look at the test conducted in the b) graph of both Figures 24 and 25
will give the answer to the steeper slope. Following from the graph we see that if
current is held constant and voltage is seen to increase, then resistance must also
increase (V=IR). This leads us to conclude that the field must also be increasing (E =
V/d in a parallel plate capacitor).
I
V
tDB
R
tDB
t
t
+
e-
e-
e-
e- e-
tDB
tDB
t
t
+
e-
e- e-
E
Iconstt.
e-
e-
_
ee- e- e- e- e-
e-
_
_
Figure 26: Electron trapping in oxide (PMOS device)
Figure 26 shows electrons traveling from the substrate to the poly across the
oxide. However, not all electrons are able to traverse the entire distance of the oxide
due to interface traps, oxide defects etc that lead to trapped electron charge building
33
up over time in the oxide layer. As can be seen over time this additional negative pole
requires a greater amount of field strength to surmount. This is noticeable in all
oxides, but if the occurrence is great enough it can ultimately lead to premature oxide
breakdown. The Fab 2 oxide is seen to trap less charge and have a higher average
breakdown time, leading to higher values of Qbd.
2.2 Poly-dot Test Structure Characterization
In evaluating GOI it is important to have a short flow device that can be run
relatively quickly and return results from experiments in a timely manner.
poly
oxide
p-sub wafer
chuck
NMOS
poly
oxide
n-well
nsub wafer
chuck
PMOS
A = 91326.9 um2
(a)
(b)
Figure 27: (a) Design layout and (b) Cross sectional schematics
34
For our purposes a wafer covered with Poly-dots shown in Figure 27 was used, to
minimize processing time and limit the number of processing steps each wafer
encountered, as each step is truly a variable. Both p and n substrate wafers were
chosen to represent NMOS and PMOS devices respectively, as opposed to only pwafers with an additional n-well implant to create PMOS devices.
Two initial lots of 12 wafers, one n and one p, were processed to establish a
baseline for the Poly-dots oxide performance against production devices and its use as
a valid test vehicle representative of production oxide quality.
2.2.1 Capacitance-Voltage Results (CV)
Inline measurements, i.e. values taken with in the foundry clean room area by
process engineers immediately following the given process step, of the Poly-dots
showed an average oxide thickness of 12 nm. To be certain, bench test CV
measurements of the Poly-dots were also performed on 6 wafers: 3 sites each topcenter-flat (18 sites). A -6 to +6 DC ramped voltage was applied with a superimposed
100 mV p-to-p (100 kHz) signal. Results showed calculated thickness values less than
5% deviant from the 12.2 nm spec, shown in Figure 28. The curves shown are the
average of the above mentioned 18 sites with a standard deviation of less than 0.01pF
35
– again smaller than the expressed accuracy of the device – essentially all material
measured the same.
36
270.E-12
25C
250.E-12
25C w/200C pos bias
Capacitance (F)
25C w/200C neg bias
230.E-12
(a)
210.E-12
190.E-12
170.E-12
-7
-5
-3
-1
1
3
5
7
Voltage (V)
270.E-12
Capacitance (F)
250.E-12
25C
230.E-12
25C w/200C pos bias
25C w/200C neg bias
210.E-12
(b)
190.E-12
170.E-12
-7
-5
-3
-1
1
3
5
Voltage (V)
Figure 28: CV sweep a) Poly-dot psub b) Poly-dot nsub
37
7
Table 2: CV thickness results – test vehicle
psub
nsub
C ox = 260.23 pF
C ox = 262.01 pF
ε o = 8.854x10
ε o = 8.854x10 −12
−12
ε r = 3.82
ε r = 3.82
A = 91326.9 um 2
A = 91326.9 um 2
t ox = 11.78 nm
t ox = 11.88 nm
The above tox values in Table 2 are calculated using equation (5). The
disturbances in the CV plots, and inability to generate a low frequency plot, could
possibly be attributed to a phenomenon called “Blooming”, a type of edge effect
pictured in Figure 28.
-6 V
-6 V
+6 V
-6 V
++++++
++++++++++++++
e- e+++
++++++
a)
b)
c)
Figure 29: a) No booming b) Blooming c) Guard rings
38
e- e+++
Blooming, the result of additional carriers drawn to the capacitor interface,
can be corrected with the use of guard rings. The expected scenario with an applied
bias is shown in a). However the true capacitance measurement can deviate, as in b),
with the effect of field fringes drawing additional carriers from the substrate creating
a non-symmetric parallel plate capacitor. The problem is corrected with the addition
of guard rings, large ring shaped structure surrounding the poly dot capacitor. The
guard rings are always biased with an opposite polarity to the poly-dot bias. During an
ideal CV sweep the rings are swept at the same time as the capacitor structure, in the
reverse direction.
Measurements are limited by the availability of equipment and although guard
rings are in place, at this time implementing a reverse ring sweep in conjunction with
the standard poly-dot bias is not possible. With inline measurements from the Fab
corresponding to our CV calculated thicknesses, it appears that the blooming is
having little effect on the Cmax value and it has been deemed appropriate to move
on.
2.2.2 Time-Dependant Dielectric Breakdown (TDDB)
A constant current of 365 μA, corresponding to a density of 0.4 A/cm2, was
forced at the poly while the chuck was held at ground.
39
20
18
16
(a)
| Voltage |
(V)
14
12
10
Q bd avg: 8.01 C/cm2
Std: 0.508
8
6
4
2
0
0
5
10
15
20
25
time (s)
20
18
16
(b)
Volatge (V)
14
12
10
Q bd avg: 7.07 C/cm2
Std: 0.777
8
6
4
2
0
0
5
10
15
20
time (s)
Figure 30: TDDB of Poly-Dots a) NMOS b) PMOS
40
25
The wafers received backgrind, a process of grinding the backside of the wafer
to reduce the overall wafer thickness and create a good electrical contact to the wafer
backside (substrate) via the chuck of the tester. The voltage across the resulting
capacitor is measured as time progresses. Results are shown in Figure 30.
The relatively low Qbd values with respect to the production oxide are most
likely due to the extreme size of the poly-dots structure, with an area over 5x greater
than the scribe sites. A larger area oxide is much more likely to contain defects and
the ratio is not considered to be one-to-one. To be sure it was necessary to perform a
ramped current density test to verify the behavior of the oxides current conducting
capability matching the scribe capacitors. Within the area of interest the poly-dots
appear to have very similar current conduction behavior to Fab 1 and Fab 2 oxide.
The Poly-dots have shown to represent an acceptable test vehicle for the production
oxide.
41
CHAPTER III
EXPERIMENTAL PROCESS MODIFICATIONS
3.1 GATE-OX Furnace
Oxide can be formed in several ways; the process evaluated here is thermal
oxidation:
Si solid + O 2 − > SiO 2 solid
and
(6)
Si solid + 2H 2O − > SiO2 solid + 2H 2
It is a combination of a wet and dry process, proceeding by the inward motion of the
oxidizing agent through the oxide layer shown in Figure 31.
Figure 31: Oxide Growth
42
A simplified representation of the GATE-OX Furnace is shown in Figure 32.
Wafers are loaded and rest in the center through the duration of the furnace cycle.
Figure 32: Simplified representation of a GATE-OX Furnace
To evaluate the effects of the furnace on GOI, three experimental processing
splits were chosen, two of which are given below in Table 3. The third is identical to
the standard Fab 1 flow with a load/unload temperature of 600oC.
43
Table 3: Gas/Temp Flows
44
normalized flow
N2
H2
O2
(a)
(b)
center
source
load
normalized time
Figure 33: Fab1 load and unload process (a) gas flow and (b) temperature
Figure 33 is a graphical representation of the Fab 1 furnace load and unload
process with gas flow shown in a) and temperature in b). The sudden drops in the
temperature section of the graph correspond to the door of the furnace opening for
loading and unloading wafers.
The following graphs in Figure 34 represent experimental furnace process
results for standard Fab 1 8000C wafer loading (full temperature and gas profiles
shown in Figure 33), new 6000C wafer loading, and standard Fab 2 process.
45
20
18
16
(V)
14
12
| Volatge |
(a)
10
Q bd avg: 6.55 C/cm2
Std: 0.710
8
Q bd avg: 10.39
C/cm2
6
4
Q bd avg: 9.22 C/cm2
Std: 0.601
2
0
0
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
time (s)
20
18
(b)
16
Volatge (V)
14
12
Q bd avg: 8.38 C/cm2
Std: 0.968
10
8
Q bd avg: 8.35 C/cm2
Std: 1.55
6
4
Q bd avg: 10.88
C/cm2
2
0
0
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
time (s)
Figure 34: Experimental Furnace process results for standard (red) 6000C (blue) and
Fab2 (green) - (a) NMOS (b) PMOS
46
The red curves represent the standard Fab 1 process, blue curves represent the
600oC process, and green curves represent the Fab 2 process. Unfortunately inline
measurements of the Fab 2 oxide show an average thickness 18% thinner than
desired, 10 nm instead of 12.2nm. Given this, it was determined by the Engineering
staff that copying the Fab 2 process was not currently possible at Fab1 and the data
would be disregarded with the focus shifted to the remaining two splits.
In both n and p substrate wafers the calculated average Qbd was higher for
the 600oC process. It can be seen graphically that at any given point before
breakdown the voltage carried by the standard processed sites is higher than the
600oC process, showing that the standard grown oxide is trapping and retaining more
electrons than the new oxide. Both Qbd averages and graphical data show that the
average breakdown was clearly much higher for the new process. Studies have shown
that recrystallization occurs at 6000C on the underlying substrate and regrowth
proceeds towards the surface with all annealing complete in a matter of minutes [18].
47
3.2 PRE-GATE Clean
After evaluating the furnace process the next logical step was to assess the pregate deposition clean. Chemical quality was first analyzed. Elemental contaminants in
all samples from chemicals used at X-Fab were <0.010 PPB [6].
A comparison of Fab 2 and Fab 1 PRE-GATE clean up (C/U) was performed.
Table 4 shows the results with the major differences in blue.
Table 4: Fab 2 vs. Fab 1, wet process differences [6] [9]
SC1, “standard clean 1” (also called RCA1 or APM) is an Ammonia Hydroxide
(NH4OH) - Hydrogen Peroxide (H202) - water Mixture, typically combined in a
0.25:1:5 ratio. It is a cleaning solution used primarily to remove particles from the
surface and capable of removing surface organics. Strong solutions can etch/roughen
the silicon surface. SC1 forms a chemical oxide (hydrophilic surface) on the Si surface.
It is normally applied at temperatures between 40oC and 70oC and typically combined
48
with Megasonic agitation. A Megasonic is used to enhance particle removal from the
wafer surface by sonic pressure. Energy normally at frequencies from 500-1000 kHz is
applied to the liquid SC1 in which the wafers are immersed creating acoustic
streaming, dislodging particles down into the sub micron range.
SC2, “standard clean 2” (also called RCA2 or HPM) is a Hydrochloric Acid Hydrogen Peroxide - water Mixture, typically combined in a 1:1:5 ratio. It is another
cleaning solution but used primarily to remove metallic contaminants.
air
quick dump
overflow
Figure 35: Overflow vs. Quick-dump Rinse
49
More recently it is being replaced with alternative recipes such as those
involving variations of weak HF/HCl solutions in water. This is apparent in Fab 1’s
choice to use a combination of HCL and DI water in place of the Fab 2 SC2 clean.
After speaking with wet process engineers from Fab 1, Fab 2, and additional
external foundries, the single major differences cited as a possible GOI problem was
Fab 1’s exclusion of an overflow-rinse process. The quick-dump rinse sprays wafers
from the top of the tank. When the tank is full the bottom opens and, in a matter of
seconds, the water is removed. Both the quick-dump and overflow rinse are shown in
Figure 35.
The problem with the quick dump process is believed to be the rapid removal
of the water surrounding the wafers. Ambient air is sucked into the tank, bringing
with it any particles in the area. Since this clean is done directly before gate
deposition, these particles will be right at the gate-oxide interface and lead directly to
GOI issues. The overflow rinse continuously fills the tank from the bottom, letting
water cascade over the top of the tank and eliminating the vacuum effect of the
quick-dump rinse.
Split lots were run at Fab 1 to evaluate the quick-dump process against one
utilizing a mock Fab 2 overflow-rinse process. Additionally wafers were also run in a
Mercury with several variations of the PRE-GATE clean up. AFM (Atomic Force
50
Microscopy) was performed on wafers following the clean to determine surface
roughness (shown in nm), as this is a common PRE-GATE phenomenon that is linked
to GOI. Graphs of all splits and results are shown in below. It is should be noted that
24 wafers with 6 PRE-GATE splits were completed. 2 wafers from each split were
taken for AFM (not possible to return these to the foundry for completion) while the
rest were completed for electrical testing. The splits are detailed in Table 5.
Table 4: Experimental wet process changes
The splits were broken up into Hood and Mercury. Thus far we have only
discussed the Hood process, wafers being lowered down into a tank containing the
liquid for a certain time (followed by a Quick dump or Overflow rinse) and then
manually (some times with automation) lifted into another tank. With the Mercury
however, wafers are placed into the machine, the operator shuts the door and presses
51
go. All rinse and chemical dip steps are done within the machine. Essentially, if the
Mercury is calibrated correctly, it should give the same process run to run, without
the element of human (operator) error.
A break down of the splits is as follows: for the Hood process STD is the
standard PRE-GATE clean and QD is the Quick dump Rinse, both shown in Table 3.
For the Mercury STD is again the process shown in Table 3, Hot SC1 is in reference to
the temperature of the applied SC1, however instead of the Fab 2 recipe 500C it was
decided to use 750C.
Hood
wafer
Mercury
wafer
Figure 35: Hood vs. Mercury
52
HF/H2O2 is a combination of a suggestion by a manager at Fab 1 and a
modified version of a surface roughness remedy from article [5]. A mixture of
HF/H2O2 is applied to the wafer surface just prior to the final rinse and dry. Cool start
will be discussed later.
It is now very important to look at the method of testing in more detail, to
better understand the graphical results that will follow. AFM wafers were removed
from the foundry proper after PRE-GATE processing, the remaining wafers were sent
on through the line. AFM measurements were taken in three locations on the wafer,
top, center, and flat (shown).
top
center
flat
Figure 36: Wafer roughness pattern
53
With the exception of the Hot SC1 split, which had no predictable behavior
whatsoever (this was expected as Hot SC1 is considered a very bad, very
unpredictable idea), all wafers showed a distinct difference in top-center-flat
roughness. The Standard Hood process is shown alone in Figure 38 to illustrate the
phenomenon with the use of a linear line fit.
14
12
Qbd (C/cm2)
10
center
8
flat
6
4
top
2
0
0
0.05
0.1
0.15
0.2
0.25
Average Roughness (nm)
Figure 37: Standard Hood Split showing top-center-flat variation
The Qbd value referenced against each roughness measurement is the average
of 4 sites (from the approximate area of the AFM measurement) on a completed
54
wafer. It is obvious that an element of uncontrolled error has been introduced in this
measurement process, but this is currently the only available possibility to obtain a
roughness vs. breakdown for the foundry at this time. The complete set of split results
are given in Figure 39 and 40.
14
12
Qbd (C/cm2)
10
8
QuickDump - psub
6
OverFlowRinse - psub
4
QuickDump - nsub
2
OverFlowRinse - nsub
0
0
0.05
0.1
0.15
Average Roughness (nm)
Figure 38: Hood C/U split results
55
0.2
0.25
14
12
Qbd (C/cm2)
10
8
Standard - psub
Hot SC1 - psub
6
HF/H2O2 - psub
cool start - psub
4
Standard - nsub
Hot SC1 - nsub
HF/H2O2 - nsub
2
cool start - nsub
0
0
0.05
0.1
0.15
0.2
0.25
Average Roughness (nm)
Figure 40: Mercury Pre-Gate Clean (C/U) split results
As hoped, the Quick Dump Hood results show a much greater spread in Qbd,
while the Overflow Rinse process shows tighter Qbd and a lower roughness value at
any given point. The surprise of the experimental results was in the Mercury with a
process called “cool start”. This was a change proposed by the wet process engineer at
Fab1, simply applying the Mercury recipe at a lower temperature.
56
14
12
Qbd (C/cm2)
10
8
cool start - psub
6
cool start - nsub
4
OverFlowRinse - psub
2
OverFlowRinse - nsub
0
0
0.05
0.1
0.15
0.2
0.25
Average Roughness (nm)
Figure 39: Cool Start vs OverFlowRinse
Figure 41 shows the best of the Hood process (OverFlowRinse) vs. the best of
the Mercury process (cool start). The cool start shows both less top-center-flat
roughness and improved Qbd and is considered to be the best result of all splits.
57
3.3 GATE/PRE-GATE Combined Split
The final split was conducted on 4 production, customer material, lots of 25
wafers each. Given the success of the 600oC furnace process on this technology and
with concurrent investigations on other technologies, Fab1 had at this point
introduced the process as standard so the 800oC (previous standard) process would not
be available.
Table 5: Final Experimental process change results
Production material is tested in the Fab on a very large scale using parametric
tests that can be executed very quickly in fractions of a second on multiple sites per
58
wafer (the average values shown are from 5 sites per wafer, top, center, flat, left, right
- on all odd or even wafers). Therefore a CV temperature stress test (approximately 1
hour per site) and a full Qbd breakdown profile (approximately 60 seconds per site)
are not feasible. The results shown above show two standard parameters used to
evaluate transistor oxide.
contact - gate
contact - substrate
oxide
p-sub wafer
220 um
chuck
80 um
NMOS
contact - gate
contact - substrate
oxide
n-well
contact
chuck
Figure 40: (a) Design layout and (b) Cross sectional schematics
To understand the production tests in detail we revisit figure 17, now pictured
in Figure 42. BVGOX is the breakdown of the gate oxide (N for NMOS, P for PMOS).
Using a voltage ramp at the transistor gate, the “BV” voltage value is taken when a
current of 1μA is measured through the oxide. In production material 1μA flowing
through the gate oxide might as well be a short. TGOX is the gate oxide thickness (N
59
for NMOS, P for PMOS), derived from a capacitance measurement taken from a
voltage bias of the gate into accumulation (ie: no CV sweep). Odd wafers are from the
hood, and even wafers were sent to the Mercury.
For the project to be successful ultimately the end of line parametric test
values need to show improvement. Unfortunately from Table 6 those values did not
change by any significant degree.
60
CHAPTER IV
CONCLUSION
As mentioned above the final combined GATE/PREGATE split did not yield
any significant differences. However the new 600oC Furnace process was an extreme
success, with greatly improved oxide breakdown values and has been implemented as
a permanent standard process in Fab 1. The PRE-GATE clean process showed better
than standard oxide breakdown with the new Mercury cool start process on test
material, but mixed results on production material. As such, the PRE-GATE step will
not have any permanent fixes from this thesis. While long term characterization and
time-consuming testing shows improvement on the tested wavers, this thesis has
shown that the results obtained do not necessarily transfer well to the mass
production floor, nor are reflected in results obtained from fraction of a second
testing.
This thesis has discussed and completely characterized a 12.2nm gate oxide
used in large scale IC production, using multiple forms of stress testing. A Poly-dot
test vehicle with 12.2nm gate-oxide was discussed and completely characterized. This
test vehicle and its characterization in this paper will be in place for future
experiments should it be needed for additional short-flow testing. Wafer fabrication
61
gate-oxide furnace fundamentals were covered in detail and several new processes
were tested. Additionally the pre-gate oxide deposition silicon clean up steps were
analyzed in two separate cleaning machines with several new processes initially
evaluated and characterized.
It is unfortunate that the final split did not show improved breakdown
performance on production material, but it is important to note that those tests were
run without an 8000C furnace baseline to determine the effect of the new furnace
process alone. This work however will exist as an excellent starting point for any
engineer at Fab 1 interested in improving on or characterizing a transistor gate-oxide
since it provides more detailed test results than what is available from production
tests.
62
RESOURCES
[1] A.S. Grove, Physics and Technology of Semiconductor Devices, New York, NY:
Wiley, 1967.
[2] S. Wolf, Silicon Processing for the VLSI Era-Volume 1, Sunset Beach, CA: Lattice
Press, 1988.
[3] S. Wolf, Silicon Processing for the VLSI Era-Volume 2, Sunset Beach, CA: Lattice
Press, 1990.
[4] S. Wolf, Silicon Processing for the VLSI Era-Volume 3, Sunset Beach, CA: Lattice
Press, 1996.
[5] Ben G. Streetman and Sanjay Banerjee, Solid State Electronic Device, 5th Edition,
Prentice-Hall of India, New Delhi, 2001.
[6] S. Campbell, The Science and Engineering of Micro Electronic Fabrication, Sunset
Beach, CA: Lattice Press, 1996.
[7] Behzad Razavi, Design of Analog CMOS Integrated Circuits, New York, NY:
Wiley, 2001
[8] JESD35-A: JEDEC STANDARD - Procedure for the Wafer-Level Testing of Thin
Dielectrics. http://www.jedec.org/
[9] K. Yamabe and K. Taniguchi, "Time-dependant dielectric breakdown of thin
thermally grown Si02 films," IEEE Trans. Electron Dev., ED-32 (1985).
[10] H. Lee, C. Lee, H. Jeon, D. Jung “The Influence of Cyclic Treatments with H2O2
and HF Solutions on the Roughness of Silicon Surface,” Korean Chem. Soc., 1997
Vol.18, No. 7.
63
APPENDIX A
THE FERMI LEVEL AND BAND DIAGRAMS
The probability of an electron occupying a given energy state E is given by the
Femi-Dirac distribution function f(E), as shown below in the Figure.
Figure 41: Fermi-Dirac distribution [16]
The Fermi level EF, at an absolute temperature T, yields a probability of ½ of
occupation by an electron. A special case at T = 0 shows for E < EF the probability is 1,
and E > EF the probability is 0. At temperatures greater than 0 there will be some
probability f(E) that electrons will occupy energy states above EF, however with the
symmetry of the function there will also be a probability (1- f(E)) that energy levels
below EF will be empty.
64
Figure 42: Band Diagrams [16]
Band diagrams, in the Figure above, provide a good visual aid in further
understanding the space occupied by electrons. Semiconductors and Insulators have a
very similar structure at 0K, both have valence bands filled with electrons and empty
conduction bands. The main difference is the size of Eg, the energy gap from the
valence to conduction band. The lesser band gap in semiconductors permits a larger
number of electrons to be promoted from the valence to conduction band providing a
more significant current flow for the same applied energy.
65
Figure 43: Metal Band Diagrams [16]
Metals at 0K may exist with partially filled conduction band or overlapping bands
shown in the figure above.
A Combination of both the Fermi function and the above band diagrams are
used to give the most comprehensive picture of semiconductor electron behavior. The
Fermi function’s graph is turned on its side and placed next to the band diagram. For
intrinsic silicon, shown on the left hand side in the below Figure, the concentration
of holes in the valence band is equal to the concentration of electrons in the
conduction band.
66
Figure 44: Intrinsic and n-type Fermi Levels [16]
For n-type silicon the Fermi level is raised closer to the conduction band,
giving a greater probability of an electron’s occupancy in the conduction band, as the
material has been doped with charge carriers. Since f(E) is symmetric around EF there
will also be fewer available holes in the valence band.
67
APPENDIX B
DESCRIPTION OF WAFER SCRIBE LINES
Scribe lines are by definition the area of a processed silicon wafer that will be cut to
separate out individual die (individual chips for packaging). A more detailed
description of this should begin with a discussion about the difference between
Parametric and Functional testing shown in Figure.
Packaged IC
Silicon wafer
(a)
(b)
Figure 45: Parametric vs. Functional Test
68
Parametric testing is conducted at the wafer foundry prior to the wafers being cut
into individual die. These tests are meant to evaluate the quality of discrete devices
(shown in (a) ie: transistors, capacitors, diodes, resistors etc) used within each die. The
test structures themselves are located in the scribe lines between individual die shown
below in Figure. These individual elements are fabricated at the same time, using the
same process steps, as the die but have connections accessible to foundries test
engineering staff.
probe
scribe line test module
pin
pin
pin 1
sourc
pin
gate
oxide
p-substrate wafer drain
(b)
(a)
Figure 46: Location of scribe between individual die
69
The data collected is one way to guarantee that the elements used with the chip are
continuing to meet acceptable levels of sheet resistance, capacitance, breakdown
voltage, channel length, conductance etc. The Figure above in (a) better illustrates
the location of scribe lines and shows a testers probe card setting down on the bond
pads, (b) gives an idea of what could possible be connected to the pads, in this case an
NMOS transistor. Typical parameters measured would include threshold voltage,
drain-source current, drain-source breakdown, gate-oxide capacitance, gate-oxide
thickness, gate-oxide breakdown, transconductance, effective channel length, and
body effect parameters.
die
completed wafer
packaging
IC
Figure 47: Packaging individual die for Functional test
70
Functional test can be done before or after packaging, but they are conducted on the
die itself, measuring non-discrete parameters (Flip-flop functionality, amplifier
frequency response etc).
71
PERMISSION TO COPY
In presenting this thesis in partial fulfillment of the requirements for a master’s
degree at Texas Tech University or Texas Tech University Health Sciences Center, I
agree that the Library and my major department shall make it freely available for research
purposes. Permission to copy this thesis for scholarly purposes may be granted by the
Director of the Library or my major professor. It is understood that any copying or
publication of this thesis for financial gain shall not be allowed without my further
written permission and that any user may be liable for copyright infringement.
Agree (Permission is granted.)
_____Adam J. Williamson_________________________
Student Signature
_____11/23/06_____
Date
Disagree
(Permission is not granted.)
_______________________________________________
Student Signature
_________________
Date